1. Field of the Invention
The present invention generally relates to a method and a circuit for demodulating digital signals, and particularly relates to a method and a circuit for demodulating digital signals which are a mixture of different signals having different modulation schemes applied thereto.
2. Description of the Related Art
When a signal having a temporal mixture of different modulation schemes such as BPSK, QPSK, and 8PSK applied thereto is to be demodulated, a digital-signal demodulation circuit needs to be designed for such a purpose.
FIG. 1 is a block diagram of an example of a digital-signal demodulation circuit which demodulates a signal that has a temporal mixture of different modulation schemes applied thereto.
The digital-signal demodulation circuit of FIG. 1 includes a tuner 1, an A/D converter 2, a timing-reproduction circuit 3, an automatic-gain-control unit 9, an analog filter 10, a forward-error-correction unit 11, and a carrier-reproduction unit 12.
The carrier-reproduction unit 12 includes a complex multiplying unit 4, an 8PSK-phase-comparison unit 5, a loop filter 6, a number-controlled oscillator 7, and a sin-and-cos table 8.
When a signal having a temporal mixture of BPSK, QPSK, and 8PSK applied thereto is supplied, the tuner 1 performs down-conversion of the supplied signal, and attends to synchronous signal detection so as to output I and Q analog signals. The A/D converter 2 receives the I and Q analog signals from the tuner 1, and converts the analog signals to digital signals to output I and Q digital signals.
The timing-reproduction circuit 3 receives the I and Q digital signals from the A/D converter 2, and reconstructs timings of the I and Q digital signals. The complex multiplying unit 4 corrects a phase of a symbol of the I and Q digital signals supplied from the timing-reproduction circuit 3 based on signals indicating the amount of phase correction. Such signals indicating the amount of phase correction are provided from the sin-and-cos table 8, which will be described later. The 8PSK-phase-comparison unit 5 receives the I and Q digital signals having the phase thereof corrected by the complex multiplying unit 4, and detects a phase difference of the symbol of the I and Q digital signals.
The digital-signal demodulation circuit of FIG. 1 reproduces a signal having a temporal mixture of BPSK, QPSK, and 8PSK by using the 8PSK-phase-comparison unit 5. In the following, a description will be given with regard to how to reproduce a signal having a temporal mixture of BPSK, QPSK, and 8PSK by using the 8PSK-phase-comparison unit 5.
FIG. 2 is an illustrative drawing for explaining how to reproduce a signal having a temporal mixture of BPSK, QPSK, and 8PSK by use of an 8PSK-phase-comparison unit.
As shown in FIG. 2, an I-Q plane is divided into eight areas. Each of the eight areas is further divided by half, one half representing positive polarization and the other half representing negative polarization.
When an input symbol x is located in the area (a) shown in FIG. 2, for example, an angle between a vector a0 and a vector x0 extending from the origin to the symbol x can be regarded as a phase difference. Further, a polarization that is predetermined for a given area as shown in FIG. 2 is output as a polarization of this area. When an input symbol is located in another area, a phase difference can be determined in the same fashion.
With reference to FIG. 1 again, the loop filter 6 applies smoothing to the signal supplied from the 8PSK-phase-comparison unit 5 where the signal indicates the phase difference as previously described. The loop filter 6 outputs the smoothed phase-difference signal. The number-controlled oscillator 7 supplies an oscillating signal to the sin-and-cos table 8 such that a frequency of the oscillating signal varies depending on the smoothed phase-difference signal. Based on the supplied oscillating signal, the sin-and-cos table 8 outputs signals indicative of the amount of phase correction that is to be made to the I and Q digital signals. These output signals are supplied to the complex multiplying unit 4.
The automatic-gain-control unit 9 receives the I and Q digital signals from the complex multiplying unit 4, and generates a signal indicative of size of the symbol of the I and Q digital signals. The generated signal is supplied to the tuner 1 via the analog filter 10.
The digital-signal demodulation circuit of FIG. 1 uses a feedback loop comprised of the complex multiplying unit 4, the 8PSK-phase-comparison unit 5, the loop filter 6, the number-controlled oscillator 7, and the sin-and-cos table 8, thereby attaining carrier reproduction. Further, another feedback loop is implemented by the tuner 1, the A/D converter 2, the timing-reproduction circuit 3, the complex multiplying unit 4, the automatic-gain-control unit 9, and the analog filter 10, and serves to control levels of the input signals to the complex multiplying unit 4.
In this manner, the complex multiplying unit 4 outputs signals that have been subjected to timing reconstruction, carrier reproduction, and input-level control, and these output signals are supplied to the forward-error-correction unit 11 to be subjected to error correction. After the error correction, signals are output as demodulated signals.
In the digital-signal demodulation circuit of FIG. 1, the 8PSK-phase-comparison unit 5 processes any signal by treating it as an 8PSK signal when detecting a phase difference of a symbol of I and Q digital signals. Because of this, a lower limit of a C/N ratio for carrier reproduction is around 10 dB, which is determined by use of 8PSK. In general, however, a lower limit of a C/N ratio for carrier reproduction is about-1 to 0 dB for 8PSK and 2 to 3 dB for QPSK. Despite these lower limits, carrier reproduction may become impossible for BPSK and QPSK when a C/N ratio falls below 10 dB in the digital-signal demodulation circuit of FIG. 1.
Accordingly, there is a need for a method and a device for digital-signal demodulation which can demodulate a signal having a temporal mixture of different modulation schemes even when a C/N ratio is relatively low.